1. Field of the Invention
The present invention relates to a method for forming semiconductor device isolation regions to electrically isolate a semiconductor device constituting a semiconductor integrated circuit.
2. Description of the Prior Art
There has been increased capacity of VLSI (very large scale integrated circuit) such as a DRAM (a dynamic random access memory) or an SRAM (a static random access memory) by four times every three years. At present, a DRAM which is mainly manufactured has the capacities of 256 Kb and 1 Mb. There has earnestly been examined a DRAM having the capacities of 4 Mb and 16 Mb which will be the mainstream in future. Probably, there will be developed a DRAM having the capacities of 64 Mb and 256 Mb.
A semiconductor device constituting an integrated circuit is made fine, so that integration can be improved in a limited chip area as described above. By way of example, the minimum dimension of a MOS (metal oxide semiconductor) transistor used in an 1 Mb DRAM is a little less than 1 .mu.m. In future, the above-mentioned minimum dimension will surely be reduced to 0.5 .mu.m and further to 0.25 .mu.m. Similarly, it is required to reduce device isolation regions for higher integration. In addition, it is necessary to reduce an isolation width from 1 .mu.m to about 0.5 .mu.m.
In general, the device isolation region is formed by a selective oxidation method. The selective oxidation method comprises steps of patterning and opening a silicon nitride film which covers a silicon substrate, and selectively oxidizing the surface of the exposed silicon substrate so as to form a silicon oxide film which is an insulating film.
According to the above-mentioned method, however, a region covered by the silicon nitride film is also oxidized at the time of selective oxidation. Consequently, there is caused the spreading of the silicon oxide film which is called a bird's beak. As a result, there cannot be obtained a fine isolation region in accordance with a mask size. In other words, referring to the selective oxidation method, the fineness of the device isolation region is limited. Therefore, the integration will not be improved in future. In addition, it is required to perform oxidation for hours so as to obtain an oxide film having a constant thickness in such a manner that sufficient insulation characteristics can be obtained. Furthermore, the oxidation causes a volume to be increased so that a stress is applied to the silicon substrate. Consequently, defects are caused to deteriorate device characteristics.
There has been proposed a trench burying isolation method as a device isolation method in place of the selective oxidation method having the above-mentioned drawbacks. The trench burying isolation method comprises steps of forming a trench on a silicon substrate with use of a resist pattern formed by lithography as an etching mask and burying the inside of the trench with an insulating film such as a silicon oxide film or the like.
The known references on a device isolation technology are as follows.
1. "A NEW TRENCH ISOLATION TECHNOLOGY AS A REPLACEMENT OF LOCOS" PA0 2. "A PRACTICAL TRENCH ISOLATION TECHNOLOGY WITH A NOVEL PLANARIZATION PROCESS" PA0 3. "BURIED-OXIDE ISOLATION WITH ETCH-STOP (BOXES)" PA0 4. IBM Technical Disclosure Bulletin, Vol. 23, No. 11 April 1981. PA0 5. IBM Technical Disclosure Bulletin, Vol. 24, No. 7B December 1981.
H. Mikoshiba, T. Homma and K. Hamano PA1 IEDM Technical Digest, 1984 P578 to 581 PA1 G. Fuse et al. PA1 IEDM Technical Digest, 1987 P732 to 735 PA1 ROBERT F. KWASNICK et al. PA1 IEEE ELECTRON DEVICE LETTERS. Vol. 9, No. 2, February 1988.
While each device constituting a semiconductor integrated circuit is arranged very densely in a limited chip area, the density of a device is not constant on the inside of a chip. By way of example, a 4 Mb DRAM has a memory cell portion in which an isolation distance between adjacent devices is a little less than 1 .mu.m, and a peripheral circuit portion in which the isolation distance between the adjacent devices is several .mu.m or several tens of .mu.m. In a device isolation process, it is required to form isolation regions having various widths in the same steps.
FIGS. 3(a) to 3(d) show the state in which large and small isolation regions are formed by a conventional trench burying isolation method in the same steps. There will be described the conventional trench burying isolation method with reference to FIG. 3.
(1) First, a resist pattern (not shown) is formed on a silicon substrate 21 in a lithography step. Then, a small trench 22 having a width W1 and a large trench 23 having a width W2 are formed with use of the resist pattern as an etching mask. The width W1 of the small trench 22 is the minimum and the width W2 of the large trench 23 is the maximum in an integrated circuit fabricated on the silicon substrate 21. The small and large trenches 22 and 23 have a depth d. The width W2 of the large trench 23 is greater than twice the depth d (see FIG. 3(a)).
(2) A silicon oxide film 24 having a thickness t2 is deposited on the silicon substrate 21 by a chemical vapor deposition method (hereinafter referred to as a CVD method) (see FIG. 3(b)).
The silicon oxide film 24 is also deposited on side walls of the trenches 22 and 23 at almost the same speed as on the surface of the silicon substrate 21. Consequently, the small trench 22 is entirely buried at a thickness of half the width W1. In case of the large trench 23 having the width greater than twice the depth, it is required to deposit the silicon oxide film 24 having a thickness which at least corresponds to the depth d in order to entirely bury the trench. As a result, it is required that a thickness t of the silicon oxide film 24 necessary to simultaneously and entirely bury both trenches on the silicon substrate 21 is not smaller than the depth d of the trench.
Although the surface of the silicon oxide film 24 is comparatively flat in the small trench 22, the flatness is reduced as the width of the trench is increased. As shown in FIG. 3(b), a difference D in stage corresponding to the depth d is formed in the large trench 23.
(3) To eliminate the difference D in stage, a resist pattern 25 is formed in the large trench 23 in the lithography step. The above-mentioned step is carried out in such a manner that the silicon oxide film in the large trench 23 is not removed in a step of removing the silicon oxide film 24 in a device region. Of course, it is desired that a thickness t3 of the resist pattern 25 is almost equal to the depth d of the trench and a width W3 is not more than a value obtained by subtracting twice the thickness t2 of the silicon oxide film 24 from the width W2 of the large trench 23. After the resist pattern 25 is formed, a resist or another spin coating film 26 is formed on the resist pattern 25 to make the surface thereof flat (see FIG. 3(c)).
(4) Finally, the spin coating film 26, resist pattern 25 and silicon oxide film 24 are etched at an equal speed until the surface of the silicon substrate 21 is exposed in the device region. Thus, the device isolation process is completed.
According to the trench burying isolation method, only the trench region, which is formed on the silicon substrate with use of the resist pattern formed in the lithography step as the etching mask, becomes an isolation region. Consequently, the isolation width can be reduced to the limit of the lithography. Therefore, the trench burying isolation method is suitable for a device isolation method of a semiconductor integrated circuit which has been improved in integration.
However, the conventional trench burying device isolation method comprises a lithography step of forming the resist pattern 25 in order to eliminate the difference D in stage of the silicon oxide film 24 in the large isolation region 23 in addition to a lithography step of defining the device isolation regions 22 and 23. In other words, it is required to carry out the lithography step twice in total. In addition, it is required to accurately arrange the resist pattern 25 in a concave portion of the silicon oxide film 24 in the large isolation region 23 in the latter lithography step. Consequently, a precise mask alignment is needed. In the case where the lithography step is added in a process for fabricating a semiconductor integrated circuit, the time required for the process is increased and the yield on a chip is lowered. Finally, a manufacturing cost is increased. Therefore, it is required to avoid the addition of the lithography step as much as possible.